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The FPGA Implementation Of Broadband PA Adaptive Digital Pre-Distortion

Posted on:2014-02-03Degree:MasterType:Thesis
Country:ChinaCandidate:X R LiFull Text:PDF
GTID:2248330398470602Subject:Electronic Science and Technology
Abstract/Summary:PDF Full Text Request
At present, the wireless communication technology is developing very fast. To get higher channel capacity and spectrum effectiveness, Modern wireless communication systems widely use high-order modulation modes that have higher spectrum efficiency but are very sensitive to the power amplifier’s nonlinear distortion, such as QAM, QPSK and so on. High-order modulation technologies have higher PAPR, so they are vulnerable to the effects of nonlinear distortion of the power amplifier. Therefore, reducing the power amplifier’s nonlinear distortion is very important. As the most effective power amplifier linearization technology, digital pre-distortion technology has attracted much attention, and at the same time, because of its good performance, easy to implement, the low cost and other advantages, digital pre-distortion has become the mainstream of the power amplifier linearization solutions.This paper discussed and researched the FPGA implementation technology of digital pre-distortion. Based on the baseband-radio frequency integrated hardware platform, the digital pre-distortion algorithm was realized using of FPGA hardware logic and embedded platform. The main work and innovation points are as follows:1. The power amplifier’s odd-order nonlinear memory polynomial model was studied, and according to the algorithm structure, the algorithm’s implementation on FPGA was divided into several modules. According to the parameters of the hardware platform and the on-board FPGA, ADC and DAC chips, the pre-distorter module, the ADC interface module and the DAC interface module were designed in detail. 2. The functions of delay estimation, coeffients computing and coeffients update were realized with C on the MicroBlaze based embedded platform. A coeffients estimation algorithm optimized for the DPD module was proposed, which could reduce the memory usage and computing time effectively. A power precorrection method was proposed, which could ensure the output power was stable when updating the coeffients.3. The performance of the algorithm was verified on the built digital pre-distortion system platform, and the test results are analyzed. Test results showed that the digital pre-distortion design achieved the desired targets.
Keywords/Search Tags:PA, DPD, FPGA, MicroBlaze
PDF Full Text Request
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