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Research On Low Power In3D Applications Based On Embedded Moble Devices

Posted on:2013-01-30Degree:MasterType:Thesis
Country:ChinaCandidate:W HuangFull Text:PDF
GTID:2248330395973342Subject:Computer application technology
Abstract/Summary:PDF Full Text Request
With increasing interest on porting PC-developed3D applications to mobile device which is battery powered, it is a strong demand for achieving the energy-saving. Currently, there exist two kinds of architectures:traditional CPU architecture and more popular CPU-GPU heterogeneous architecture. However, there are rarely helping for existing low-power technology in both architectures’3D applications. It need further research about low-power in3D applications for embedded mobile devices.For traditional CPU architecture, in order to use the low-power technology DVFS, the most of current methods are predicting the workload of future frame by the information of current frame for3D applications. However, it cannot accurately predict the workload due to using the larger particle size of information granularity. Combined with existing research, if we extract the information of frame using kernel function, the accuracy of workload prediction will be greatly improved. For the popular CPU-GPU heterogeneous architecture, there is little research on low-power via software method because of imperfect low-power model. When a large capacity data need be processed for3D application, the bandwidth of PCI-E will become a bottleneck between CPU processes and GPU processes. Hence, in order to better improve the research, if we process the data combined with the GPU features, which reasonably assigned to the workload on CPU and GPU that provide a parallel operation mechanism, the power consumption of entire system will be reduced to the utmost.According to research problems, the main works and achievement of this paper is as follows: 1. For CPU architecture, extract the hierarchy of kernel and analyze the main kernel which consume a lot of time.2. In order to eliminate the overhead of frequent adjustment the frequency of CPU, we propose an improved version of the greedy algorithm.3. For CPU-GPU heterogeneous architecture, due to reasonably allocation the workload to CPU and GPU, we propose a data sub-block program which combined with the feature of GPU-Cache line alignment.4. In order to simplify the discussion, we convert the optimization model of power consumption into the model of time optimization which provides rigorous reasoning and analysis process.
Keywords/Search Tags:3D applications, low-power, CPU architecture, CPU-GPUheterogeneous architecture, DVFS, data sub-block
PDF Full Text Request
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