Public Key Cryptography Research On Parallel Processing Algorithm And Architecture

With the rapid development of wireless communication technology, its security problem has raised more and more concern. The security level of wireless communication is low due to its characteristics, that is to say, one can intercept data sending or receiving by others via wireless technology as long as he has wireless access equipment. It is rather a great loss for the correspondent, if the eavesdropper gets some key information such as Bank account password, personal identity and so on. Therefore, it is necessary to encrypt the wireless communication data. In fact, in order to ensure the safety of users’ data, many relevant standards have been proposed such as802.11, WAPI which rule the wireless encryption/decryption agreement while communicating in the field of wireless local area network. In these agreements, safe authentication is an important part.In cryptography field, public key algorithm can provide very safe authentication mechanism due to its characteristics. The calculation of public key cryptography algorithms, however, is a very complicated process, which needs a lot of long integer modular operations such as the1024-bit modular multiplication and modular addition. As a result, the general platforms take a long operating time to realize the authentication process based on public key algorithm especially small wireless devices such as network Access Point. The delay of authentication process will have great influence on users who use wireless communication applications in the future, such as IP call, HD video broadcast and so on.Therefore, this paper researches on the high performance and low cost implementation of public key algorithm including two aspects. First of all, this paper, from the aspect of algorithm, studies the parallel processing algorithm of public key algorithm based on multicore processor, including the parallelism of Montgomery modular multiplication, point addition and double point based on ECC. In addition, this thesis concretely analyzes the hardware design of modular multiplication, and proposes a kind of high speed and low area structure of Montgomery multiplier, which laids a solid foundation for the development of low cost and high performance public key processorFinally, in order to verify the proposed theory and the efficiency of hardware design, this thesis designed a public-key oriented4-core processor. It is fabricated by using standard TSMC65nm LP CMOS process. The test chip result shows that the proposed processor only needs small area and power consumption but can achieve very high throughput rate. Therefore, it means the research in this thesis is effective. Last but not least, the4-core processor can be well fit for small wireless communication equipment of the next generation, so it has a good application prospect.