Research On High-bandwidth Exchange Of Peripheral Data And Processing Techniques For Multi-processor System-on-Chip

With the development of integrated circuit technology, multi-processorsystem-on-chip (MPSoC) technology which is increasingly applied in variousfields of life and production has become a hot topic of the current research.MPSoC provides a good solution to the complex application of high-densitycomputing. In order to achieve balanced multi-processor programming, theapplying program is granularly divided into the smallest. Hence the dataexchange of multi-processor becomes more frequently, and thecommunication bandwidth has become a very important factor in determiningthe overall performance in the system-on-chip. In this dissertion, the work ischosen to a heterogeneous prototype system of MPSoC which is anapplication in high-density-oriented computing. Targeting at the problem ofdata exchange of peripheral data of the prototype system, the work wascarried out mainly in the following aspects.In the application of embedded MPSoC, the communication architectureof a shared bus and two-dimensional mesh-NoC was selected. The mappingmethod was researched and analyzed in the multi-FPGA prototype design.Forthe high data bandwidth and consumption of low chip pins in the inter-chip, a mixed communication scheme was proposed which control signaltransported asynchronously and main data based on high bandwith Rocket IO.The inter-chip communication module based on packet connected circuitprotocol is designed and implemented. The experimental result shows thatwhen the ratio of Communication pins in the total of pins is4.29%,so thepins are high in utilization efficiency in the four FPGA chips is high.In order to meet the input and output of high-bandwidth data in thesystem of MPSoC, the Gigabit Ethernet was selected. The interface ofEthernet based on packet connected circuit protocol is designed. Theexperiments show that the method not only meets the requirement of real- time and high bandwidth communications, but also helps FPGA verificationin the preliminary project, and it improves verification efficiency.In order to meet the high real-time requirements, the design of FIRfiltering cluster was designed to accelerate data signal processing. Thematrix transpose is completed in the storage array. The module of20-orderFIR filter is used repeatedly. The FIR filter completes the filtering operationof12×1024in parallel processiong mode.For the interface designed in this dissertation, The acheme of integrationand verification was discussed in the system. The interface design has beenintegrated in a heterogeneous MPSoC system. The demo was also achievedbased on an application of image processing.