Study Of RapidIO IPcore Software And Hardware Co-design And Verification Method

The traditional hierarchical bus can not meet I/O performance requirements of the future high-performance embedded system and more efficient signal processing and data transmission. Then RapidIO interconnect technology emerged. The features of high bandwidth, low latency, high efficiency and high reliability provide an ideal solution for system interconnection with embedded systems. It is possible to implement RapidIO as an interface in the high performance design of SoC in order to satisfy the demands of system based on several advantages of high-speed serial bus RapidIO. In this dissertation, hardware and software co-design and verification methods were studied, and based on two platforms, verifified RapidIO IPcore.After deeply researched on RapidIO protocol, the briefly description of design of RapidIO IPcore would be achieved, including the design of internal logic and the transport layer module, the register module, the register management module, the physical layer module, the clock and reset module, the user module. The dissertation mainly focused on the verification methods of RapidIO IPcore. The verification rule had been settled firstly and the simulation condition and FPGA condition of verification around RapidIO IPcore had been constructed at the same time. The function and performance could also been verified by implementing the testcases which have been developed based on both simulation and FPGA verification platform.The verification results show that the functions are correct in accordance with the RapidIO2.1protocol version. Verification could reach higher signal and functional rate of coverage. Its performance criterion definitely match the theoretical analysis and could been considered as the basement of the future design and verification for SoC cores basing implementation RapidIO.