The Data Transfer Design Based On FPGA RapidIO

With the rapid development of the computer industry and the chip industry in recent years,the development of embedded systems has become very important.the demand of high speed,high performance and high reliability bus technology has been urgently needed also.The traditional bus technology has become more and more difficult to support the demand of the market.The traditional bus used previously can not satisfy the requirements of the stability and reliability of the high speed signal transmission in the communication industry.Therefore,RapidIO emerged as a development requirement.The purpose of the research is applied to interconnect in the embedded device.Therefore,the RapidIO protocol is usually selected for the processing of high rate data in FPGA.This paper mainly studies the application of RapidIO protocol and the process of DDR3 receiving data and transmitting data and storage.After that,this paper introduces the background and research significance,the development process of RapidIO,at the same time introducing the current situation and application of bus technology at internal and external.Then,it mainly introduces the relevant interface meaning of RapidIO protocol,network topology design,data transmission method,protocol layering,port logic operation specification and other aspects to introduce the protocol in detail.In the protocol specification overview,the logical layer,transport layer,physical layer,and the specific implementation of the resolution of the layer protocol under the layered architecture are analyzed.The package format and transaction type of RapidIO and controller correlation and error recovery management are also described in detail.By analyzing the design principles,we can understand the function design process and further understand the implementation process of RapidIO protocol and the implementation process of DDR3 controller module.Then the implementation part of the protocol describes how the maintenance operation access the configuration register space,how to implement the interaction between the remote and local transactions,and the implementation of the special DOORBELL transaction operation.Then it introduces the IPCore generation method of the memory module,and describes how to perform DDR3 command,read,and write timing operations.By displaying part of the RTL code,it demonstrates the process of realizing DDR3 accessing data.The RapidIO protocol verification process mainly introduces the simulation verification platform,the simulation verification platform construction process,the RapidIO protocol HELLO packet format simulation implementation and DDR3 reading and writing simulation process.The validation section also provides detailed parsing of the package format and physical layer control fields for MAINTENANCE request transactions,SWTITE request transactions,and RESPONSE response transactions.After analyzing the simulation results,we understand the difference between RapidIO protocol and other similar bus protocols and the advantages in bus transmission methods,and eventually lay the foundation for further in-depth understanding of embedded technology.