Low Cost Of Usb2.0 Host Controller And Driver Design

USB has become a widely used serial interface standard as its outstanding feature, such as higher transmission speed, hot-pluggable, flexible and so on. Almost there is electronic equipment where there is USB. Because of that, lots of human and material resources are invested by many companies or research units into the USB-related hardware and software research and development, hoping that their products add USB function to improve the competitiveness of products, in addition to the USB to achieve the required performance, but not increasing too much cost. Therefore the low-cost USB2.0host controller issue is proposed.This paper first discusses the specifications of USB2.0and UTMI, and then analyzed the main types of host controller (UHCI, OHCI, EHCI, xHCI and other vendors or individual self-defined) on the market and specification standard or hardware, software design. As the basis for the introduction of new low-cost USB2.0host controller hardware and software design.Hardware design section contains architectures of host controller, software and hardware register interface and sub-modules function and state transition, such as AHB slave interface module (usb20_sl_if), USB2.0DMA controller module (usb20_dma_ctl), buffer management controller module (buffer_manage), protocol layer controller module (usb20_host_pl), USB2.0host register controller (usb20_host_reg) and USB2.0port controller module (usb20_port_ctl). They are implemented by Verilog HDL.Software design section only includes the design of hardware-related parts of the host controller driver, the hardware-independent USB stacks and client driver can get from Linux kernel. Host controller driver includes some sub modules, such as USBD interface module, root hub management module, the data transmission module, interrupt management module and so on. They are implemented by C language.In addition, qualitative analysis of this solution has lower hardware cost than UHCI, OHCI, EHCI, xHCI host controller and almost the same performance in mass store device class. To improve the performance of this host controller, there are two innovations:first, using asynchronous clock domain ping-pong buffer by two single-port SRAMs;second, using pipelined parallel operation between DMA read or write transfer and USB transaction, thereby enhancing the USB bus bandwidth utilization or lower the system bus bandwidth requirements.Finally, do a completely verification of low-speed, full-speed, high-speed, bus reset and DMA operations by the automation of the BFM-based method. After the synthesis of the host controller RTL, its area is only7.5k gate count (not include SRAM area).The results show that this solution is feasible, meets the needs of low cost and high performance.