The Development And Software Corroboration For A High Performance Host Controller For SDXC Card

With the continuous development of electronic products, more and more increasingly rich content is loaded on. This content are including pictures, songs, games and videos with various formats, which required the product with high performance and capacity. Meanwhile, the consumer electronics products are developed with direction of miniaturization, low-power and low-cost, which resulting in memory device with limited capacity is integrated. For the expansion of the storage capacity, design a interface to an external storage device is simple and economical solution.Currently, SD card is the most widely used external memory cards, superiority for small size, high capacity, high performance, security, and so on. It has been widely used on digital cameras, digital cameras, smart phones, PDA and other consumer electronic products. To fulfill the rapid developed demand of capacity, access speed and power consumption, SD Group(Panasonic, SanDisk and Toshiba) and SD Card Association launched SD3.0 specification, in 2009. The SDXC(Extended Capacity SD Memory Card) is proposed in SD3.0 specification. The SDXC card is compatible with SD2.0 specification, meanwhile the speed(the maximum data transfer rate is up to 104MB/s) and capacity(up to 2TB) of SDXC card has greatly improved. In terms of low-power, the SDXC card can support a lower operating voltage(1.8V).To complete this thesis, a high-speed SDXC card host controller is developed. The main topic of this thesis includes:1. Study the specification of SDXC card, including internal registers, communication protocols and the data format. The differences between SDXC card and SD2.0 card are focused. Contained with CRC7 and CRC16 circuitry, a separate protocols controller module is designed for implementing a physical layer protocol interface achievement.2. To support the fastest speed of different cards, two clock signals is import into the host controller. In order to improve the data transfer performance between system and card controller, the data transmission is implemented through OCP bus during DMA operation. A variety of techniques is involved to reduce power consumption. The detailed analysis for each technique is introduced in this thesis. And the negative impact caused by these techniques and the approach is also introduced.