The Research And Design Of DES/3_DES Algorithm IP Core Based On AMBA Bus

With the information technology and network development,how to ensure the security of information transmission is an emergency solved problem.As the most secure and reliable protection mechanism,encryption technology has become the core of information security work.As the most widely used and most successful algorithm in scientific cryptography development process,DES algorithm is still widely used in satellite communications,national defense,communication protection,commercial finance and other fields.The triple DES algorithm improves security strength by adding the key length, overcoming the attacking danger of DES algorithm.Based on the audio/video SoC design project,according to the typical IP core design process,using the new digital EDA platform of Synopsys company,this paper finished the design of DES/3_DES IP core with the standard AMBA bus interface.The IP core supports encryption/decryption operation and data processing rate achieves 1.6Gbits/s and 615Mbits/s under two algorithms.It’s satisfy the demand of many systems.Using the ideas to design the direct mapping module and the state machine cycle control module respectively,it can use one hardware computation module to implement different modes of different algorithms by the different settings of the configured parameters in control module,strengthen the portability and flexibility of this IP core in different application environments.Meanwhile specifically design the parity module and weak key module to detect the key,effectively strengthen security strength of the algorithm.Moreover,the IP core has three interrupt output signals,can be well integrated in the SoC by interrupt system and hardware DMA requests.Based on the AHB bus complete the module level functional verification and testing points analysis.Using the chip level verification platform to finish the coverage drived functional verification.The results show that coverage can reach more than ninety-nine percent.Besides adopt the formal verification tool Formality to do the equivalence verification,ensure the consistency of the design before and after logic synthesis.Finally build FPGA prototype verified board and finish the prototype verification,using FPGA hardware platform validate functional correctness of design.Finally,complete logic synthesis based on 65nm CMOS process library of TSMC and finish the low power design by using part of the gated clock insert technology,the results show that the dynamic power of IP core is only 377.6314 uw,the area is only 22661.28 um2.Adopt the worst working conditions(125℃,1.08 V)to do the timing verification,the results show that the IP core meets the timing requirements in 500MHz frequency and the longest critical path is consistent with the design analysis.Contrast with currently realized designs in china,the above results have obvious superiority in frequency, area and power consumption.At present,as encryption/decryption engine,the IP core has been obtained good integration in ZW100 SoC system,effectively ensure the safety of the chip system.Meanwhile with standard AMBA bus interface,the IP core can conveniently get further applications in the SoC design project about safety-oriented communication,e-commerce,security video monitoring and other kinds of applications,has a good market application value.