Design And Implementation Of Multi-core DSP L1D Cache Supporting Directory Protocol

DSP is a special processor to realize the high-speed and real-time digital signal processing,which has the characteristics of good programmability and low power dissipation and has become the major computation engine in the field of various embedded applications.With the continuous progress of integrated circuit technology and the increase of application requirements,multi-core DSP has become the mainstream of development to provide higher performance in a limited power budget.Because the multi-core DSP usually has a mixed memory structure with scratchpad memory and multi-level Cache hierarchy,a new requirement for its data coherence maintenance of the multi-core shared memory is presented.Design a L1Data Cache(L1D Cache)to support efficiently the consistency protocol of the mixed memory is of great significance to improve the performance and programmability and scalability of the system.Based on the architecture and the design requirement of its scalable directory protocol of the multi-core digital signal processing chip Y-DSP developed independently,this paper puts forward the overall scheme of its L1D Cache which supports the directory protocol of the mixed memory architecture,and then completes the detailed design and verification of L1D Cache,and last carries out the performance analysis and logic synthesis based on 40 nm technology.The main research contents of this paper include the followings:Firstly,based on the overall architecture and mixed memory structure of Y-DSP,the former memory coherence management scheme of software programming is introduced.The functional requirements and overall design scheme of L1D Cache are put forward based on the extended directory protocol to support DMA operations.Secondly,the detailed design of L1D Cache is implemented based on MSI protocol,which includes Cache Tag,data memory organization and Cache controller and so on.It not only realizes the pipeline operation function of memory access instructions but also deals with the coherence transactions generated by the multi-core memory accesses and DMA operations,and maintains the Cache coherence.Thirdly,the testbench of two cores of memory system has been established based on SystemVerilog language.The function verification is finished by the directional and random test vectors.The results show that L1D Cache design fulfils its functions.Lastly,the detailed performance of L1D Cache is analysed,and the logic synthesis has been carried out based on 40 nm technology.Compared with the former software coherence maintenance strategy of Y-DSP,the design in this paper saves 6.12% of the area overhead.For discrete memory request operations,this scheme saves a lot of time overhead brought by flush operation based on software maintenance strategy and effectively maintain the data coherence in the multi-core DSP.