Study Of 3d Network-on-Chip

The scaling of microchip technologies has enabled large scale system-on-chip. Buses and point-to-point connections would not adapt the continuous development of system-on-chip. On-Chip-Network is easy to extend the address space, and it can provide good parallel communication ability; using packet switching as basic communication technique and adopting Globally Asynchronous Locally Synchronous communication mechanism will completely stove the problem caused by on-chip-bus from the view of architecture. Transmission delay is the important criterion of network performance, which is mainly resulted by the routing algorithm of On-Chip-Network, affecting the performance of On-Chip-Network. According to the emergence of 3D IC technology, 3-Dimensional Networks-On-Chip (3D NoC) problem is becoming a hot topic.3D NoC architectures offer better performance than 2D NoC in multi-processor system. This paper studied kinds of topology structures for 3D NoC (3D Mesh topology, BFT topology, shuffle exchange topology, De Bruijn graph topology and XNoTs topology). Then the paper introduced routing technology apply to 3D NoC (such as wormhole exchange technology and virtual channel technology) and routing algorithms (dimension ordered routing algorithm, turn model routing algorithm, planar adaptive routing algorithm), and proposed XY-YZ routing algorithm based on the 3D Mesh structure. The algorithm is a kind of adaptive, deadlock-free and minimal routing algorithm, and proof of deadlock and fault-tolerance analysis is presented. Finally, the algorithm simulated on 3D Mesh topology network to evaluate and analyzed the performance through Noxim experiment platform. The experimental results showed that XY-YZ routing algorithm has good performance in throughput, average latency and power dissipation.