High Speed And Low Power Sram And Design

With manufacture process scaling down, embedded memory is becoming a more and more important part in SoC design. About 90% area in SoC chip will be taken by different kinds of memories in 2010. SRAM takes a critical role in SoC owing to its high density and speed, low power consumption and its manufacture compatibility with logic process. In recent years, portable devices and high performance processor become popular. Since it brings higher requirement to SRAM design, high performance and low power consumption become the mainstream of chip.This thesis makes a summary about SRAM memory development in domestic and abroad at first. Based on the principle of memory operation and main peripheral circuits study, with TSMC 90nm technology, a SRAM configured as 1.5Kx32 is designed for TT240, a smart card IC designed by SST, Inc. In the design process, SRAM is parted to several array segments by bit-line divided and word-line divided technology. It uses tracking cell to copy loadings on bit-line and word-line. Tracking cell structure generates the global control signal by means of adding dummy columns and dummy rows and using word-line feedback. The SRAM also uses a voltage-latch sense amplifier with a pre-charge structure and uses multi-level decoders to raise system operation capability. In layout design, it brings up a new kind of SRAM core cell in and under 90nm manufacture process. The new cell optimizes the structure and sharing method, so that it saves the area. In addition, to meet the data safety of TT240, it separates the external power and internal cell power. It can clean up all data by pulling down all cells power.Based on above skills, the circuit and layout is finished and the SRAM has been tape-out in a test-chip. Silicon data has proved the chip works. SRAM working voltage is 1.20V-1.32V. Clock frequency is at 50MHz. Maximum read and write average current is 2mA. Maximum access time is 7ns. This SRAM reaches the target of high speed and low power.