Research And Realization Of Sense Amplifier For Wide-Voltage Static Random Access Memory

With the rapid development of consumer electronics products such as smartphones, tablets, the demand for high performance and low-power SoC continues to rise. Designing SRAM that work at wide voltage become the focus of industry's research. Sense amplifier which is among the critical path circuits of SRAM determines its speed, power and stability, requiring careful design. The main challenges focused in wide voltage sense amplifier are:(1) at low voltage, memory cells structures that are single-ended reading appears, and traditional differential sense amplifier is not compatible with them; (2) In order to ensure a low voltage detection yield for SA, the bit line swing is too large.The main research work includes:(1) summarizes and compares the commonly used differential, single-ended sense amplifier circuit. Considering the area, performance and stability, small signal detection sense amplifier is more suitable for high-voltage SRAM design; a full swing detection scheme is more suitable for low-voltage SRAM design. (2) A wide-voltage low-power pseudo-differential sense amplifier that can choose suitable reference voltage by itself according to its polar of offset is proposed. Compared with conventional pseudo-differential sense amplifier, the proposed SA adopts calibration based on voltage compensation which can effectively reduce the offset voltage at high voltage; Compared with full-swing sense amplifier RSSA, this SA lowers the pre-charge voltage which can reduce the swing of bitlines at low voltage. When the supply voltage is 0.8-1. ?, compared to the traditional pseudo-differential SA, the offset is decreased by more man 36.7%; 0.6-0.7 V, the bit line swing is even reduced to about 50%. The overall performance is at least optimized 12.6% at wide voltage.A 64 Kbits SRAM macro is implemented in SMIC 40 nm LL CMOS technology. The test results indicate that this SRAM design coupled with MBIST achieves 215MHz frequency at 1.1V and 43MHz at 0.6V. Compared with SRAM design based on RSSA, the SRAM macro of with proposed SA in this thesis achieves 12.2% reduction of power consumtion at 0.6V and 13.9% reduction at 1.1V.