The Dvb-s2 Demodulator Key Algorithms And Vlsi Implementation

The digital technology on modulation and demodulation has been quickly developing in the recent years as well as error control coding and decoding, which push forward the digital video technology immensely that also benefits from the great progress of VLSI design.A series of digital video standards aimed to fully cover the broadcasting network all over the world has been introduced by ETSI, such as DVB-C/T/H/S and they have been evolved into the second generation. DVB-S2 promises to yield better transmission performance than DVB-S with more flexible configurations and LDPC coding scheme, which has drawn much attention for the receiver implementation.DVB-S2 is widely used in broadcasting, interactive services,news gathering and other broadband satellite applications.The DVB-S2 compliant receivers are more of an accretion on supporting 8PSK mode in the market and the case of without pilot and lower code rates configurations are commonly ignored, while high-order modulation mode are going to be popular as high data rate and professional applications are dramatically desired. Low code rates and high-order modulation schemes mean much worse channel conditions and higher complexity. Therefore, the demodulator should be elaborately designed with these factors considered to enable its better performance.The thesis mainly includes the following results,(1)The prevalent transmission standards over satellite links are comprehensively compared after extensive and in-depth investigations, and frame structure and channel coding scheme of DVB-S2 system are described briefly to indicate its advantage.(2) The channel characteristics are analyzed in detail to disclose the tough possible nodes in the system design process, while the framework is also investigated.(3) The tx-rx model is constructed via the analysis on channel impairments, and the key modules of demodulator are extensively inspected and devised. Better schemes on either algorithm or implementation are proposed via fully exploring the useful characteristics abstracted from frame structure and signal constellation as well as the conventional contributions.(4) A robust and reliable frame synchronization method is developed based on pilot-symbol-assisted differential correlation and double-peak search detection. Simulation results show that perfect frame synchronization has been achieved under even the worst channel conditions specified with all the modulation modes and pilot configurations friendly supported.(5)A non-decision-directed carrier synchronization scheme is given mainly to solve the implementation complexity issue that lies in the conventional DD methods. Simulation results show that it has good estimation performance and compared with the DD ones, the NDD scheme is more attractive especially for its complexity level.(6) A more stringent cost function is applied to derive a novel DAGC iteration for the convergence of the gain factor under the analysis on the disadvantage of the conventional data-aided schemes. Numerical results show that the new scheme processes several desired features such as increased convergence speed, low complexity and all modes simply supported.(7) A signed-DD-LMS combined with signed-CMA equalization scheme is presented to compensate for the ISI introduced by echo signal inherent in the cable from LNB to tuner. The combined method is validated to be effective in relieving adverse impact of the ISI with low complexity overhead.(8) The architecture of the demodulator is provided with respect to overall evaluation scheme. It is described in VerilogHDL and validated comprising comprehensive performance test on the metrics concerned on FPGA platform using StraitixⅡEP2S180F1020C3.It is shown that the demodulator can fulfill the demodulation correctly of DVB-S2 signals.