Vlsi Implementation Of A New Generation Of Satellite Digital Tv Demodulator Key Algorithms

With the rapid development of digital communication technology, digital broadcast television has stepped into the era of digital television. With the raise of the digital compressing and coding technology, the transmission of the HDTV has been realized. The wave of knowledge technology brings the full development of a series of modern technologies, including broadcasting television, integrated circuits technology, computer science, microelectronics, information processing technology and communication technology. These technologies have been widely used by the digital television.Satellite digital broadcasting television is one of the pratical applications of satellite communication. Satellite broadcasting network has the advantages of wide spectrum and extensive covering range and the cost of communication has no relationship with the distance. Meanwhile, it can be built very quickly and provide good media for information broadcasting. But in practice the satellite channel is characteristic of very low SNR and large carrier frequency offset. Thus, it sets high requirements for designing robust receiver for satellite broadcasting signal.In this thesis, we set the DVB-S2 protocol as research background. Starting from the principle of modulation technique and combing with the further research on satellite broadcasting transmission channel, we focus on the several key function modules of the receiver which could demodulate digital satellite broadcasting signal of DVB-S2. We propose a design scheme for the inner receiver in digital satellite television receiver, which consists of system architecture, physical frame synchronization, timing recovery loop, matched filter and carrier recovery loop with large acquire range at low signal to noise. And then, following the ASIC design flow, we implement the inner receiver with the goal of high performance, low cost and low power. Finally, we validate the function of receiver on FPGA development board. Following is the main contribution of this thesis:(1) Research on the current development of digital television and digital satellite broadcasting television standards in different countries of the world. Set DVB-S2 protocol as research background, we study the principle of different kinds of modulation technique and new forward error correction technique, and describe the technogical advantage of the technique and their future development.(2) Analyze the characteristics of satellite broadcasting transmisstion channel and model them on system level. Make further research on the architecture of digital satellite digital television receiver system, which mainly consists of antenna, low noise block, TUNER, digital satellite equipment controller and channel receiver. This thesis emphasizes on modeling the inner receiver on algorithm level, which consists of anti-alias filter, timing recovery loop, physical frame synchronization, carrier recovery loop and matched filter.(3) With the model of satellite transmisstion channel, we compare various design schemes on the platform of inner receiver model and analyze performance effects among different modules. Based on the simulation results, we propose a high performance design scheme of inner receiver and optimize the algorithms. The adopted scheme can acquire physical frame synchronization under large carrier frequency offset at very low SNR, thus achieve correct demodulation. Take thorough consideration into the complexity of algorithms and optimize the VLSI architecture, we reduce the hardware area of the inner receiver in VLSI implementation.(4) We analyze the principle of timing error detector and parabolic interpolator in detail. By optimizing the implementation architecture of timing recovery loop, we propose an improved design method of digital controlled oscillator according to the design spec. The timing recovery loop can recover the variable symbol rated clock from the system clock, ranging from 2MHz to 31MHz.(5) By using canonic signed digit to represent each coefficient of FIR filter and local search method to optimize the coefficients, we implement a nonmultiplier FIR filter for matched filter. Thus greatly reduce the complexity of the circuit and improve the computing precision.(6) By further analyzing the structure of the Physical Layer Header that consists of Start of Frame and Physical Layer Signalling Code, we find some useful properties that can enhance the frame synchronization and reduce the complexity of its implementation. The optimal frame synchronization can be achieved under large carrier frequency offset (as large as 5MHz at 25MSps) and low SNR threshold of -2.3dB.(7) The algorithm of the carrier recovery module is based on pilots. We optimize the hardware architecture and adopt folding technique to reuse the units in the module. Thus greatly reduce the area of the circuit and implemental complexity.