"based On The Memory Of The Optical Interconnect Architecture" Of Storage Management And Realization

With the development of hardware technologies,computer architecture has had great changes. The centre of computer system is transferring from traditional CPU, memory and network to storage system. High performance computing research is facing challenge and innovation on architecture is urgent, because the traditional computer architecture is hard to meeting the high performance computing. Therefore, based on the Dynamic Self-Organized Computer Architecture Based on Grid-Components (DSAG) concept,"The remote memory box based on optical interconnection"is presented. In the architecture, components in different catalogs are parted, while the ones in same catalog are congregated. This architecture can be enabled by optical interconnect instead of electronic interconnect. The system is featured by high bandwidth, powerful, flexible."The Control and Interconnect Model"is the important portion of the Memory Box, which completes the interconnection of the"Client"and the"Memory array", and translates the virtual page number into the physical page number, and manages the Memory array. In this thesis"The Control and Interconnect Model"can be researched and designed. Following contributions are presented in this thesis.1. The"The Control and Interconnect Model"overall design plan and design methods was proposed. Hardware and software co-design methods was used in the system, which based on FPGA-based embedded system development platform, both meeting the demand of high-speed and high efficiency, but also taking into account the future of intelligent design scalability.2. Memory Box system has the three major protocols - remote memory access agreement, remote server memory interconnection agreements and access memory array agreement, which were studyied and defined. The design of the"memory array Access Protocol model"and the verification of the correctness of its function were done.3. The memory management unit fitting for the system has been researched. Firstly, using FPGA to complete the design of the TLB and PT; secondly, using the embedded software to complete the effective management of the memory array. At present, the two-map showing method has been adopted. Because it is hard to design this part of the system, it still needs to be more in-depth study.4. The system verification platform has been structured, and the method of the system verification has been designed. Finally, the system are simulated and tested.