Research On The Key Technology Of New Memory Application In FPGA

With the development of integrated circuit manufacturing technology, the advanced ASIC manufacturing technology has been used for FPGA. Because of its low non-recurring engineering (NRE) cost and short time-to-market, FPGA is gradually replacing ASIC as the main implementation strategy for integrated circuits. For the andvanced CMOS technology below 0.13?m, FPGA mainly uses static random access memory (SRAM) as the programming technology.-Since SRAM is volatile, and the non-volatile memories, such as EEPROM, Flash, antifuse, have poor compatibility with the standard CMOS technology and can not be integrated into the SRAM FPGA chip, FPGA usually requires a non-volatile memory outside of the chip to save the configuration information during poweroff. But this will cause the configuration information to be easily stolen and brings security issues. In addition, the SRAM progammable element generally has six transistors, and the large size brings more area overhead. The static power of SRAM cells in FPGA increases too fast when the technology scales, limiting the elevation of integration density and performance of FPGA. Directed at the problems in development of FPGA, several solutions based on the novel memories have been put forward from different angles in this dissertation.Novel resistance random access memory (RRAM) has been proven to have good compatibility with the standard CMOS process, and the application of RRAM into FPGA has become the hot research field at home and abroad. As to the security issue of the SRAM programming technology, a non-volatile SRAM cell of 9T2R and its corresponding operation algorithm have been put forward for the FPGA applications in need of high secuity and fast power-up. With the proposed RRAM programming technology, the partial reconfiguration is very quick and the multi-context configuration is efficient in the hardware cost for dynamic reconfiguration. The corresponding FPGA building blocks, including look-up table (LUT), programmable interconnect resources and configuration memory, and a low-power mode are also presented. The testchip in SMIC 0.13?m logic technology has verified the function of the proposed RRAM programming technology.The lookup table in the conventional FPGA usually adopts the static CMOS logic approach, which is often slow in performance, large in area, and power-consuming. By combining the dynamic CMOS logic and the 1T1R RRAM cell, a dynamic non-volatile look-up table is proposed with the RRAM programming technology and some circuit optimizations. The proposed RRAM non-volatile look-up table has better performance, lower power, and higher reliability than the previously reported MRAM counterpart. Compared with the static look-up table, the dynamic look-up table is dependent on the clock, which makes the design relatively complicated, but it provides a potential solution for high-performance FPGA. The testchip in SMIC 0.13?m logic technology has verified the function of the proposed dynamic non-volatile look-up table based on RRAM.Novel two-transistor embedded DRAM (2T eDRAM) adopts the standard CMOS process, and the cell area is small. The 2T eDRAM is often employed to replace SRAM where high-density storage in the advanced technology is needed. As to the issues caused by the large size of the SRAM programmable element, the 2T eDRAM is proposed to replace SRAM as the programming technology. The restore algorithms and high threshold transistors are introduced to overcome the data reliability problem of the 2T eDRAM programmable element. The key modules of the corresponding FPGA, including look-up table, programmable interconnect resources and dual-port block RAM, are presented. Besides, a CAD flow is used to verify the density and performance advantages of 2T eDRAM FPGA over SRAM FPGA, and the testchip in SMIC 0.13?m logic technology has verified the key modules of 2T eDRAM FPGA.