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Group Transformation Consisting Of A Variety Of Bch Code And Fpga-based Realization

Posted on:2008-07-15Degree:MasterType:Thesis
Country:ChinaCandidate:Y YuanFull Text:PDF
GTID:2208360215953796Subject:Physical Electronics
Abstract/Summary:PDF Full Text Request
The purpose of communication is to send message reliably which the other side doesn't know (sometimes secretly) in time. If there is disturbance in the channel, the message may make a mistake. In digital communication, we usually use err correcting code technique to control the mistake. It may improve the reliability of data transmission.BCH code is a kind of widely used group code which can correct several mistakes. It has good performance in error correcting. It's important technique of 3G operation. The thesis thoroughly analyses the rule of BCH code and introduce the coding and decoding theory of BCH code. Besides iterative decoding and step by step arithmetic, it put emphasis on the decoding theory based on group translation. It does carefully research in weight distributions, bit error rate, coding and decoding of BCH code. It completes software emulation of BCH code as well. At the same time it expounds the decoding error principle with example. In the way of MATLAB emulation it also compares the decoding performance of different BCH codes.Traditional means of coding and decoding of BCH code is to work out the determinant. So it has extremely great calculation complexity and is hard to using it for the project. Now we give a new method of coding and decoding of BCH code which is based on the group translation. It has simple algorithm and is easy to apply to hardware. It fits for different projects such as electronics communication and computer. So it has good foreground. Based on the method the thesis works out the coding and decoding module of BCH code on FPGA. Among them the 4 error correcting module of BCH code creatively using the clock frequency departing module to make up the lack of hardware space. The module is downloaded on the Cyclone chip EP1C3T144C8 and is successfully debugged. It enormously cut down the bit error rate and it has good pragmatic value.
Keywords/Search Tags:error correcting code, BCH, FPGA
PDF Full Text Request
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