B3G The Base Station Hardware Platform Design And Implementation

UESTC is in charge of the downlink of the B3G project that bases on FPGA. The system needs a hardware platform to verify both algorithm and FPGA logic program. This paper is mainly concerned with the design and implementation of this unique platform.First stage, the system specifications and total physical layer parameters are brought out to show the overall platform restriction. Additionally, interfaces between physical layer and MAC layer, physical layer and RF front-end are specified.Second stage, the base station of downlink is dividied into several parts according to different function in data processing. After deeply analysis of data process and data transfer, this paper carries out a systematic solution in order to achieve the most optimized performance in the most economic resource occupation. The platform mentioned above is based on Xilinx FPGA Virtex-II Pro? series.Then, baseband transmission board and multi-antenna transmission board as two parts of base station platform are discused respectively.Board one, baseband transmission board, mainly responsible for unpackaging data from MAC layer and rearranging data in physical layer format. Following data stream, LDPC encode and frame interleave are needed.Board Two, multi-antenna transmission board, mainly designed to implement OFDM modulation and frame make-up. Then, baseband analog IQ signals are transmited to RF front-end.In the design of baseband transmission board, depending on the system design, several FPGA configuration modes are supported, selectable via mode pin, for instance, JTAG and Slave-serial mode. Consider schematics design, this paper is focus on design using Protel99SE development environment. Consider PCB layout, this paper puts emphasis on analysis of high speed RocketIO wiring and signal integration.In the design of multi-antenna transmission board, using similar development procedure and fundamental framework, design of digital to analog converter AD9777 is supplement to this part. In addition, peripheral circuits are shown to clarifying a brief understanding in functional diagramof clock and control module.At last, this paper mentioned hardware platform debugging and B3G TDD system field joint debugging as a summary of this paper.