FPGA Configuration Methods And Circuit Design Based On JTAG

FPGA?Field Programmable Gate Array?has high-powered and programmable advantage.Users be able to alter configuration data of FPGA to achieve designed function on the basis of their needs.At present FPGA has been widely used for major space engineerings,such as manned space,high track warning,lunar and mars exploration,Beidou satellite navigation,space station and soon.JTAG?Joint Test Action Group?is a vital module of FPGA,responsible for configuration and testing functions.External configuration data can be loaded into the programmable region of chip to implement configuration function through JTAG circuit.Also boundary-scan instructions can be executed to test the chip of internal interconnection or observe or alter the circuit behaviors,completing the testing function.As the result of designed JTAG circuit using for an aerospace-grade high-powered ten million grates FPGA,JTAG circuit of this paper has the following features compared the common JTAG circuit:1.compatibility with IEEE 1149.1 standard and IEEE 1532 standard and the ability of achieving the FPGA configuration through the two sets of criteria;2.the testing capability of the ten million grates FPGA,containing 2505bits boundary-scan chain;3.satisfying the required of the aerospace-grade FPGA,and JTAG single event functional interrupt rate reaching4.7?10^-10Upset/devices/day.Therefore,the main research work of this paper includes following.1.It lays the foundation for circuit design that reading corresponding literature,researching IEEE 1149.1 standard and IEEE 1532 standard,studying their principles,structures and the logical function of the components,and understanding the architecture and configuration principle of FPGA.2.According to the feature of FPGA,this paper designs the whole architecture of JTAG circuit and every circuit modules,including TAP Controller,ISC state machine,instruction register,data registers and so on.Some modules are verified the correctness of function.3.Because of the designed circuit working in the condition of aerospace,this paper puts forward the sensibility test system,mainly evaluating influence level of every module of JTAG circuit for SEU.The results indicate that the sensitivity of the state machine module is the highest.Finally this paper completes hardened design from system-level,circuit-level and layout-level.4.The simulations of designed-well circuit are verified.Firstly,this article verifies the circuit functions.On the one hand,test functions including SAMPLE,EXTEST,INTEST,BYPASS and so on are verified.On the other hand,the configuration behaviors of the two sets of criteria are verified respectively.Secondly,this paper simulates the main timing parameters of the JTAG circuit,containing maximum TCK clock frequency?66MHz?,TMS and TDI setup time before TCK?1ns?,TMS and TDI hold time after TCK?2ns?.Finally,the layout of the JTAG circuit is achieved.This article completes the whole design flow through above-mentioned work.Measurement results show the JTAG circuit meets the design requirements and satisfies the product indexes.Compared with the foreign product,designed JTAG circuit shows strong competitive power.It is positive to develop senior FPGA chip,promote comprehensive national strength and revitalize the famous industry.