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Gps Dual Frequency P Code Receiver Front-end Circuit Design And Realization

Posted on:2008-06-14Degree:MasterType:Thesis
Country:ChinaCandidate:Z H PanFull Text:PDF
GTID:2208360215464236Subject:Computer application technology
Abstract/Summary:PDF Full Text Request
The Global Navigation Satellite System (GNSS) can provide global coverage, continuous/all weather operation, and high navigation and positioning accuracy, and is developing quickly in recent years。Because of the modernization of GPS and constructions of other GNSS, the satellite signals used for navigation will be increased rapidly。Consequently, a multi-frequency and multi-system (MFMS) GNSS receiver is bond to be a mainstream in the near future。At Present, a significant technical difficulty in developing MFMS GNSS receiver is the lack of the suitable front-end ASIC。To lay the groundwork for the integrated orbit determination and some other related projects, a GPS dual-frequency P code receiver front-end has been developed with some common integrated circuits in the paper。The independent innovation in this paper lies in the following two points:(1) The GP2015 which is a GPS C/A front-end ASIC is used smartly for the design of the GPS dual-frequency P code receiver front-end。This front-end is a good basis for the GPS dual- frequency P code receiver。(2) A DDS frequency synthesizer is used in the circuit。It can be adapted to MFMU GNSS receiver conveniently without changing the primary components, so the compatibility of the front-end is greatly improved。A MFMU GNSS receiver design style is well embodied in the paper which is consistent with the development of the GNSS receiver。According to the related testing, the front-end has a really good practical performance。It has been applied to some related projects, and is valuable to the MFMS GNSS receiver。...
Keywords/Search Tags:front-end, dual-frequency, multi-frequency and multi-system GPS, receiver
PDF Full Text Request
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