.1.5 Bit / Pipelined Adc Typical Single-stage Circuit Structure

With the explosive development of communication system and digital signal processing technology, an analog-to-digital converter, as a interface between analog signal and digital signal, is necessary. Pipeline ADC has an excellent combination of high converter rate and high converter precision. At the same time, it has a good tradeoff between speed and dissipation, so It is widely used. A 33Msample/s 1.5bit/stage 10 bit pipeline ADC is designed and analyzed in this paper.In this paper, the performance of several classical A/D converters with different architecture is analyzed and compared. Pipeline ADC is selected for its better performance. By analyzing the tradeoff between the speed and dissipation, 1.5bit/stage pipeline ADC is adopted.The system structure is improved based on the traditional 1.5bit/stage pipeline ADC. The first 9 stages adopt the same structure after being improved, which makes the design modularized. The tenth stage just need a simple comparator which can correct the ninth stage. The improved system decreases the difficulty in designing and saves more designing time.A few system errors that are gain error, sub ADC error and sub DAC error etc are simulated and analyzed. In this paper the sources of these errors are analyzed and these errors are simulated in the Matlab/simulink environment. From the simulation result, we can know the influence from the errors to the system performance.Two error correction technologies, which are gain error correction technology and comparator error correction technology, are brought forth and applied in the 1.5bit/stage pipeline ADC. Meantime, they are simulated in the Matlab/simulink environment and the result of simulation shows that the two correction technologies can eliminate the corresponding errors.Several mainly cell circuits that are sub ADC, sub DAC and digital correction circuit, are designed and simulated.