Font Size: a A A

Research On Digital Image Compression Denoising Based On FPGA And Its Realization By

Posted on:2016-02-29Degree:MasterType:Thesis
Country:ChinaCandidate:X X SunFull Text:PDF
GTID:2208330461487667Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
Digital images for its great potential are widely used in various fields, such as defense, education, medicine, astronomy, and so on. However, various types of noise interfere images during acquisition, transfer processes caused image distortion and a large number of redundant information limits the image transmission efficiency and storage space, so how to obtain the high-resolution, high compression ratio images and improve information transfer rate are becoming an important problems placed in front of us. Hardware design and implementation of image compression de-noising method based on FPGA is proposed in order to overcoming shortcomings of software-based image processing methods. This method is ideal for some pixel-level image processing and takes into account the real-time requirements of the system.Through analyzing and sorting domestic and overseas data of image compression de-noising literature, this paper proposes a kind of image compression and de-noising system based on FPGA. The system consists of FPGA minimum system, MATLAB image compression and de-noising algorithm programming, and image de-noising system based on FPGA. FPGA minimum system mainly configured by the power supply module, reset circuit module, download circuit module, clock circuit module, serial communication modules, other external auxiliary modules and so on. In order to suppress noise, remove redundant information and better protect the image details, this paper uses median filter de-noising algorithm, fast median filter de-noising algorithm, wavelet threshold de-noising algorithm, DCT compression algorithm and wavelet compression algorithm, applying MATLAB to design upper computer program, and achieves the display of the compression de-noising images. The image de-noising system based on FPGA consists of line buffer module, FIFO module, square window generation module and algorithm module. It uses Verilog-HDL and Quartus II to have timing simulation for each module and generates timing constraints report to do specific performance analysis and description of FP GA de-noising system.The experimental results show that this system achieves all the desired requirements. Noise and redundant information are eliminated after image median de-nosing and wavelet compression, the second compression ratio got 1:11.7, the residual energy of compressed was 99.9998%, the mean square error was 0.2654 and the peak SNR was 53.8922 db. Comparison between fast median filtering algorithm and classical median filtering algorithm, we can find fast algorithm’s delay is smaller, only waitting three clock can we obtain a target output. Therefore, the fast algorithm’s performance is doubling than the classical.
Keywords/Search Tags:Image compression, Image de-noising, FPGA, Verilog-HDL, MATLAB
PDF Full Text Request
Related items