Dielectrics In Deep Submicron Integrated Circuits Manufacturing Self-aligned Contact Mechanism And Application Of Through-hole Etching Process

The contact via hole etch is one of the key processes in IC manufacturing. With the critical dimension getting smaller and the integration density getting higher, the demand for accuracy of manufacturing processes has greatly increased especially for sub-micron feature size. The self-aligned contact via hole etch process as an advanced dielectric etch process can effectively satisfy the demand of photolithography processes'accuracy, so the understanding of the self-aligned contact via hole etch process becomes necessary.The thesis describes the development history and the current status of etching process, such as the development from wet etch to dry etch, the characteristic and theory of plasma dry etch, and the development of dry etching process from PE&RIE mode to MERIE&ICP mode. It also introduces the RIE mode's theory and the F/C ratio effect on the etching rate and selectivity of dielectric etch.The thesis focuses on the study of the self-aligned contact via hole etch process in which a hardmask structure is employed. The process needs to firstly define the contact hole's size by SAC hardmask_ET, then use the hardmask to do SAC_ET, thus it can lower the requirement to lithograohy process.As the contact hole's size has important impact to the wafer's WAT and CP yield, the hole size control solution is obtained by adjusting SAC Hardmask_ET process parameters through several experiments in this thesis.To satisfy the etch selectivity requirement the SAC_ET process which will create heavy polymers is applied, but the polymer will directly impact SAC_ET itself and wafer's WAT and Cp yield. A new method is invented that can monitor and control the SAC_ET polymer distribution. Meanwhile the wafer's WAT and CP yield dependence on SAC process parameters is obtained and optimized for volumn production.