Fingerprint Identification System Based On Dsp And Rf Card Design And Optimization

There have been a lot of research achievements regarding embedded fingerprint identification in various fields, and also there are many available implementations and applications in markets as well as various hardware architectures. In recent years, many research institutions are active in the fingerprint identification solutions regarding embedded DSP, i.e. FPGA, which further promoted a variety of fingerprint recognition techniques and applications. This system mainly uses DSP chips to process the collected fingerprint images. The system design and architecture are based on research results of previous seniors. The comprehensive consideration and design of the system are based on the previous successes and failures, while taking low-power consumption, fixed-point DSP, high performance, low-cost requirements into consideration.In general, previous designs did not realize optimization of algorithm in the embedded system. Basically, they focused on debugging and adjustment of the hardware, transplanting algorithm to DSP to achieve the functions. This is only to be able to run the minimum requirements, but never a work was carried out in meeting the needs of real-time processing before the seniors graduated.The main work in this article is as follows:1. Design a high-performance hardware system cored by fixed-point single DSP, which including image acquisition, image processing, memory modules, bus interfaces and human interaction module; embed DSP / BIOS embedded real-time cores under the successful debugging of the hardware, and add the fingerprint recognition system application and thread scheduler programs.2. Complete the transplanting of algorithm based on TMS320C5510; ensure the algorithm in real-time tasks can run independently and complete testing; considering TMS320C5510 has no asynchronous UART interface, use the synchronous serial port software to simulate asynchronous environment so as to achieve communication with RF card reader. This can reduce the chip design cost and hardware complexity.3. Under the condition that algorithms and operating systems achieve stability in running the work, effectively and efficiently evaluate the bottlenecks of DSP performance. Featuring the characteristics of fixed-point DSP as the core, convert algorithm from fixed-point to floating based on TMS320C5510, optimize scheduling of algorithm in storage space, complete the system of nonlinear operation optimization from the aspects of mathematical conversion and DSPLIB interface calls.