Research On The Hardware-software Code Partition Technology Of Reconfigurable Computing Systems

As an effective technique to solve software transplantation and simplify application design,reconfigurable compiling has become an integral part of reconfigurable computing systems. Hardware-software code partition technology, which divides the code into the appropriate processing unit of reconfigurable platform to enhance the processing performance of reconfigurable platform, is one of the most important research topics of reconfigurable compiling. It needs to consider characteristics of the program code and features of reconfigurable hardware comprehensively to acquire accurate parameters of the performance of executing. However, it is hard to predict the hardware performance of code segment, especially the nested loop as the performance differences of hardware circuit converted by different design method, are very distinct. It is a difficult problem to find out a good partition method. In this thesis, we design a loop body as pipeline, combining the characteristics of FPGA, which is depth parallel pipeline.An optimizing hardware circuit design method is proposed, which considers the important factors affecting the performance of reconfigurable hardware circuit. Using the proposed performance evaluation model of reconfigurable platform, it can effectively guide the software and hardware partition. The main contributions of the thesis are as follows:1. An optimized pipeline partition method combined with the deep parallel pipeline of FPGA is proposed. It takes maximum clock frequency of pipeline, clock delay in different pipeline step and the interval of adjacent circle. Our experiments show that the method can improve clock frequency and reduce pipeline interval time;2. A design space search method under hardware resource constraints combined the optimized method of loop block and loop unrolling is proposed. The proposed method can improve the parallelism and data reuse. Our experiments show that the method can reduce external memory access and achieve multi-pipeline parallel, thereby reducing the hardware execution time.3. An improved simulated annealing algorithm is applied to the design space search model. Our experiments show that the algorithms can search near optimal circuit design in a short time.4. A parametric hardware execution time evaluation model is designed, base on the analysis of the main factors which impact the performance of reconfigurable hardware circuit. Our experiments show that the proposed model can effectively guide the hardware-software code partitioning.