Research On The Hardware-Software Code Partition Technology Of Reconfigurable Computing Systems

Reconfigurable computing, emerging as a novel computing platform, combines the programmability of the traditional general purpose processor(GPP) and the spatial execution of hardware circuits, and breaks the traditional boundary between hardware and software. By taking different special optimizations when running different application programs, it can provide both the comparable execution efficiency with application specific integrated circuits(ASIC) and the similar flexibility to the general purpose processor.In most current reconfigurable computing systems, reconfigurable hardware acts as a co-processor, coupling to a general purpose processor core(GPP-Core). The difference in the architecture makes the reconfigurable hardware suitable to execute the computation-intensive code fragments, and leave the remaining codes to GPP-Core. So a hardware-software partition is needed to determine which part of the program is executed on the reconfigurable hardware and which part is executed on the GPP-Core according to the code fragment's characteristic. And current reconfigurable hardware can only be programmed using the hardware description language(HDL) programs is another factor that limits the usage of reconfigurable computing systems.In order to automatically partition the input high-level-language program at compile time, and generate the corresponding HDL program according to the code fragments which are assigned to the reconfigurable hardware, the research work of this dissertation is focused on the following three aspects.Reconfigurable hardware modeling. In order to take an efficient hardware-software code partition at compile time, the knowledge of the underling platform's architecture is necessary. By studying the current reconfigurable hardware models, a new modeling method is proposed, which can accurately describe the reconfigurable hardware's architecture and property, and provide all the information needed by the hardware-software code partition. Automatic code transformation and circuit placement. Reconfigurable hardware executes program in the similar way to ASIC. In order to quickly and accurately estimate a program's execution time on reconfigurable hardware and the corresponding configuration time, and to improve the partition's quality, a code transformation technology is needed to automatically convert the program's source code to a circuit, which is then mapped onto a specified area of the reconfigurable hardware by using a placement algorithm. After the mapping, the execution time and configuration time can be calculated according pre-defined rules. Current reconfigurable hardware can only be programmed by using HDL programs, so the code transformation is also responsible for generating the corresponding HDL program.Hardware-software partition technology. In the reconfigurable computing systems, the GPP-Core and reconfigurable hardware are independent and can work respectively. By studying the current partition methods, a more efficient partition technology is proposed by combining task scheduling and configuration reduction technology. Use the characteristic that GPP-Core and reconfigurable hardware can work separately and the program's inherent parallelism to decrease the reconfiguration overhead, to reduce the program's execution time and to improve the system performance.The achievements and innovations in this dissertation:(1) A reconfigurable hardware modeling and description method which is based on resource type and position are proposed. Model the reconfigurable hardware's architecture according to the on-chip resources' type, position and amount. Also a hierarchical method is used to describe the established model. Experiment shows that the proposed method is workable.(2) An IP-Core based code transformation is proposed. Under the support of a pre-build IP-Core library, by replacing each node in the data flow graph with a call to IP-Core instance according to the operation of the node, a program's data flow graph is converted to a circuit automatically. After finishing the pipeline partition which makes the circuit can execute in a pipeline style, the corresponding HDL program is automatically generated. The IP-Cores' HDL programs are pre-generated, which make it very simple to generate the circuit's HDL program automatically. Because the resources used in a IP-Core are placed and routed during the IP-Core is generated, there are less hardware synthesis, place and route work needed to done during the compile process, which will reduce the compiler's execution time. Experiment shows that the proposed method can make the automatic generation of HDL program easier.(3) A placement algorithm used to mapping a code fragment onto the reconfigurable hardware is proposed. Under the support of IP-Core library and the architecture model of reconfigurable hardware, place the program's corresponding circuit which is generated using the IP-Core based code transformation, onto a specified area of the reconfigurable hardware. Compared with current task placement algorithms, the proposed algorithm not only allow the tasks communicating with each other using on-chip resources, but also can be used to place task graphs using special on-chip resources onto a reconfigurable hardware containing the corresponding special resources. Experiments show that compared with current placer in the DEA toolset, the proposed method can execute 10~4 times faster, which also proves the advantage of the IP-Core based code transformation.(4) A list scheduling based hardware-software partition method is proposed. By combining the list scheduling and code partition, the execution time estimated at compile time is used to evaluate the quality of a partition plan. In order to cover the system reconfiguration overhead using the program's useful computation, the configuration prefetch is used in the scheduling. So the program's execution can be reduced and the reconfigurable computing system's performance can be improved. Experiments show that compared with current partition method, the proposed method can reduce the programs' average execution time by over 20%.