The Reliability Research In Power Device Packaging

With increasing in the chip power and decreasing in the chip size, the thermal density increased quickly and the heat dissipation of integrated circuit (IC) has been a key problem for the reliability of the power device packaging. There are two issues to affect the power device packaging reliability. One is void growth and welding quality in the chip attachment solder layer between chip and Cu lead frame, another is the reliability and quality of Aluminium wire bonding. This thesis, based on these two issues, aims to provide reference of process parameters and theoretical basis to improve processes of power device packaging for industry manufacturing through the experiment research and finite element analysis method.In this thesis, power devices packaging technology and related reliability research were introduced firstly. For the issue of voiding in chip attachment solder layer, based on orthogonal experiment method, process parameters such as temperature, time, and pressure were investigated. Optimal parameters were obtained and effects of parameters on the void were explored. Furthermore, aluminium wire (5mil, 15mil) bonding process was also researched using orthogonal experiment method and the optimal process parameter widows were determined. The prediction model for aluminum wire (5mil) bonding based on back-propagation neural network (BPNN) was also constructed to show the inherent relationship between the process parameters and the bonding quality. Results revealed that the values of network training result are almost the same with values of the experiment, while the values of network examination have near 10% error with values of experiment.Secondly, thermal-mechanical reliability of power device packaging was researched using ANSYS finite element software. Three dimensions FEA model was constructed to analyze the temperature and stress distribution of the model. Effects of chip power, solder thickness, void position in solder joint and void percentage on temperature and stress distribution of the model were discussed. The formation mechanism of void was discussed, and some suggestions based on the FEA results for die attachment process were proposed.Finally, the thermal-mechanical fatigue reliability of die attachment solder layer was studied in detail by finite element analysis in the way of von Mises stress, von Mises plastic strain, and accumulated plastic energy density under accelerated thermal cycling loading (-55℃to +125℃, 10min ramps/20min dwells). The fatigue life prediction was investigated in volume-average-energy method by R.Darveaux. The results show that the maximum plastic stress, strain, and plastic energy were found at the corner or on the edge of the solder layer, which could lead to initial crack damage in the solder layer according to the failure analysis criterion. With increasing in temperature cycles, the stress-strain hysteretic loops of the dangerous position have a steady trend. The plastic energy accumulated within temperature cycle becomes larger while the increment of plastic energy per cycle trends to be stable. In addition, chip size has some influences on the thermal reliability. With increasing in chip size, the maximum plastic stress and strain at the dangerous position increase, which could lead to poor reliability of the die attachment.