The Design Of FPGA Based Multiple IP-video Display System

Embedded systems represent a challenging technology in the consumer, industry and academic applications. The combination of high performance from hardware with flexibility in software makes FPGA-based embedded systems as a best solution for video processing over IP system.This thesis is based on the concept of such a system, which chooses the MicroBlaze as the microprocessor and uClinux as the operating system, targeting on a Xilinx FPGA platform to realize processing multiple video streams over the Ethernet and displaying them on the monitor.The paper describes the theory background of Virtex2 Pro development board, the software core processor MircoBlaze and uClinux operating system, then presents the process of how to build the hardware and software platform, and the process of development, migration and download of the uClinux kernel.The video captured by the AXIS network cameras could be compressed in the format of MPEG-4 or MJPEG. Based on the different compress format, it is necessary to give an introduce of the corresponding Internet transport protocols. Meanwhile, the project develops two different socket applications for them to setup communications between the cameras and board. Under different parameters of resolution, compression, frame rate and the numbers of cameras, by comparing the results of runtime, package loss and CPU load to evaluate the real-time and performance of the system.Because of the expense limit of the project, MJPEG decoder is used to implement into the system. It contains the baseline process decoder and VGA display system. The software and hardware simulation is used to evaluate the possibility of the MJPEG decoder. Then it was implemented into the project as a custom IP core, and connected to the bus on different manures.