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Design And Implementation Of High Speed Burst-mode Bit-error Test System Based On FPGA

Posted on:2011-05-29Degree:MasterType:Thesis
Country:ChinaCandidate:L J SunFull Text:PDF
GTID:2178360305481971Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
Owing to the distinct advantages of Gigabit-Capable Passive Optical Network (GPON) system, GPON is begun to be applied in the access network on a large scale. The burst-mode optical receivers (BMRx) in OLT play an vital role in GPON system, its performance directly impact the data processing capacity of central office in GPON. While there are few commercial and mature reliability test equipment for GPON BMRx, as to this, in this paper a design method for burst-mode BERT for GPON BMRx Based on FPGA is put forward.The upstream data characterized by burst-mode in GPON brings two design difficulties:one is that, The transmitter of BERT should generates the burst-mode data with amplitude and phase variations to simulate the upstream data in GPON; the other is that, the receiver should be able to extract clock and recover data accurately from incoming data packets with varying phases before the payloads become valid, furthermore, the receiver ought to filter the overhead bits and execute BER statistic only for payload. So the burst-mode BERT is different from general continual-data stream bit error rate tester (BERT) both in transmitter and receiver. To sum as, The burst-mode BERT is used to measure the response time of BMRx to fulfill recovering the varying amplitudes and phases and test their reliability.In this paper, according to the characteristic of GOPN upstream, a design method for burst-mode BERT Based on FPGA was put forward. The transmitter of burst-mode BERT generates busrt-mode data with amplitude and phase variations to simulate the upstream data in GPON, the receiver can extract clock and recover data accurately from incoming data packets within 12 bits, furthermore, the receiver filter the overhead bits and execute BER statistic only for payload.The whole system can be divided into two parts:the logic part of BERT and the control system. The logic part of BERT functions as test patterns generator and error bit checker. The control system consists of a Microblaze soft processor and some peripherals. The control system is used to control the logic part of BERT and interact with upper machine.The experimental results of self loop test and applying this test equipment to 1.25G burst-mode optical receivers (BMRx) in GPON system illustrate that it has good performance and practical value.
Keywords/Search Tags:burst-mode communications, BERT, FPGA, RocketIO GTP transceiver
PDF Full Text Request
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