Analysis On FD LDMOS With P-opposite Doped Layer

power semiconductor device research has become more and more important with the rapid development of power integrated circuits,. LDMOS (Lateral Double-Diffused MOSFET) is a lateral high-voltage devices. all of its electrodes locate at the surface, thus easier to be integrated with cmos technology. moreover, it has a lot of advantage such as high break-down voltage,large gian and low distortion.so it has been widely used in RF areas. now the LDMOS design is focus on how to get high breakdown voltage with a low on-resistance,and ensure a higher stability at the same time.Field plate technology is frequently used as a terminal technology. Good field plate design can smoothing the electric, reducing the peak electric field,so lead to a low breakdown voltage and weakn the hot carrier effect. Based on this, this paper use two-dimensional simulator sofeware MEDICI to analyse many parameters of Idmos, such as high voltage field plate, the drift region, etc. The simulation and analysis in detail,SOA, high-temperature breakdown characteristics, these analysis will help designers to optimize the design of the LDMOS.The first chapter described the development of integrated circuits and power devices history, then points out the significance of power devices,Then the general LDMOS model was introduced, compared it's structure, performance and technology differences to normal MSOFET, so the pave the way to following chapters.LDMOS field plate design is an integral part of the hole design. In this paper, Medici simulation software is used to anlayse single-step field plate LDMOS performance. According to the results, the length and position of the polysilicon field plate,, the biasing and the drift doping concentration, gate oxide thickness will have a certain impact on breakdown voltage. Moreover, considering different field plate structure's temp-effect and capacitance effect, and other factors.bised on which we point out the range of convenience of different LDMOS structures and part of optimize paremeters.Subsequently, this paper calculated the LDMOS electric field and electric potential in the drift region,for Idmos which used RESURF technology, we can improve the breakdown voltage and reduce the resistance by adjusting the field plate position, length, bias and other parameters,LDMOS reliability is also a design issue that must be considered. It is not only related to the structure and the device itself, but also, manufacturing processes, application conditions and other factors LDMOS stability will face of greater challenges with the reduced size of the device,. At last,this article introduce specific effects such as Kirk effect, the parasitic transistor effect, self-heating effects and hot carrier, explian the causes of these effects and corresponding solution.