Research On Generalized Petersen Graph Based Network On Chip Architecture

Since 2001, Stanford University William J. Dally and Brian Towles proposed the concept of Network on Chip(NoC) to the present, NoC captured the attention of more and more researchers because of its great potential, relevant technology research get rapid development, has become a very active area of academic research. NoC topology is currently a research focus. NoC topology has a significant impact on network performance, communication reliability, cost and complexity of hardware implementation. Researchers in the research field of NoC have proposed a lot of NoC topology, the most commonly used are mesh and torus.Generalized Peterson graph is a generalization of Peterson graph. In this paper, we design a generalized Peterson graph based NoC architecture based on the investigation of generalized Peterson graph. According to the characteristics of the average distance of generalized Peterson graph based NoC architecture is relatively small, we first design a shortest path routing algorithm and implement in a NoC simulator. On this basis we then design a genetic algorithm-based cores mapping algorithm to optimize energy consumption of this NoC architecture.Simulation experiments show that when the traffic load is small, generalized Peterson graph based NoC architecture has a smaller data transfer delay compared with mesh and torus. In this paper, we use a multimedia application to test the cores mapping algorithm. Experiments show that the result is a fast converged and optimal solution.