Interconnect Crosstalk Estimation And Delay Optimization Based On 65 Nanometer CMOS Technology

Rapid advanced in VLSI technology has enabled the CMOS integrated circuit into nanometer process. The feature size on chip is continuously decreasing as well as the operating frequency increases, in conjunction with ASIC (Application-specific integrate circuit) develops to SOC (System on chip) and NOC (Network on chip), the crosstalk noise between the adjacent interconnect lines and interconnect intrinsic delay have become critical factors for circuit performance and reliability. Hence, it is important to establish simple and efficient models to accurately evaluate the crosstalk voltage and interconnect delay, which not only provide a reference for IC designers in high speed CMOS design to avoid logic error or functional failure, but also offer excellent advantage for the exploitation of EDA software. This paper makes a deep research and discussion for crosstalk noise and interconnect delay combined the interconnect lines characteristic in nanometer process.This paper concentrates on the crosstalk noise estimation and interconnects delay optimization based on the 65nm CMOS process, synthetically considering parasitical capacitive coupling and parasitical inductive coupling. It's organized as follows. In section II we present metrics to extract Resistor-Inductance-Capacitance (RLC) parameters and discuss the influence of frequency, copper interconnect and low-k dielectric on interconnect parameters. After analyzing crosstalk couple mechanism, a new RLC crosstalk noise estimation model is established in section III based on Devgan crosstalk model and Martin crosstalk model, which takes the inductance into account. The results compared with HSPICE show the accuracy of the proposed model. Traditional Elmore delay model, fitted Elmore delay and transmission line model are introduced in section IV, and then we integrate power and area into repeater insertion methodology along with time delay, develop a novel delay optimum model based on Lagrangian function to design the size and number of repeaters inserted. In section V, we investigate the interconnect delay variation caused by crosstalk noise. Capacitive coupling between interconnect lines lead to pattern-dependent delay is analyzed by switch factor technique from Elmore delay definition. Inductive coupling effect is also calculated by ABCD matrix method that establishes the RLC interconnect electrical equation. Then interconnect delay expression can be acquired by mathematical optimization and Pade reduced-order technique.