| With the rapid scaling down of CMOS device technology and continuously rising of VLSI working frequency, more and more functionality modules are integrated on a chip. It leads to larger chip sizes and implies an increase in the use of interconnect buses. Due to communications between subsystems (such as IP cores and micro-processors) are usually realized by interconnect buses or point-to-point interconnects, on-chip interconnects have been the IC performance bottleneck and became important consumer of chip power and area. Consequently, it is meaningful to handle power, area and performance problems brought by on-chip interconnect.According to the working mechanism and physical characteristics of interconnects, basic electrics parameter models are introduced and simple analysis are performed. This paper established repeater area model, interconnect delay model, interconnect bandwidth model and interconnect power model, and proposed an interconnect optimization model combing repeater insertion with wire sizing. This model can perform interconnect power and repeater area optimizations with the target constraints of interconnect delay and bandwidth. Deeper research on this optimization model was made through combing Low-swing technology with the previous technologies. Later we extended the research objects to on-chip buses. On the foundation of research on data transformed on buses, combing wire ordering with wire spacing, we proposed a bus optimization model with the target constraints of design rules and other conditions. Experiment results verified the validity of the proposed optimization models.In the end we performed research on temperature characteristic of interconnect and proposed a novel interconnect temperature distribution model considering via effect and heat fringing effect. Considering self-heating effect, we analyzed the effect of interconnect temperature rise on interconnect delay and optimization results based on the previously proposed model. |
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