Design And Implementation Of A Parallel Processor Based On DNA Computing

As a new type of calculation method, DNA computing has many advantages such as a high degree of parallelism, high speed, large storage capacity, low energy consumption and abundant natural resources. DNA computing algorithm is intuitively effective, worthy of further study. But DNA computer requires too much about the surroundings and is less precise than a real DNA computer should act. There are no practical DNA computers till now. Having been developed for tens of years, electronic means computing is quite mature for its high accuracy and good programmability.In this paper we show a parallel processor model, for which we design an instance with Verilog HDL and then implement it in FPGA. This model unites the advantages of DNA computing and electronic means to a.certain extent.The model includes controller, parallel storage processor, I/O system and memory. We focus on the implementation of controller and parallel storage processor, which are different from the traditional computer components. There is an instruction set for controller, containing arithmetic and logic operations and basic control commands. The parallel storage processor includes four parts: parallel storage process arry, address transformation module, data parallel input module and output module. The parallel storage process array is the main body of parallel storage processor. The other three parts are used to improve I/O efficiency of parallel storage process array. Following the idea of DNA computing, parallel storage process array is huge parallel and compute just at the memory in computation section. 4-value logic is used in input section and dichotomy in output section.This Paper mainly discusses follows: 1. Discuss an electronic parallel processor model based on DNA computing. It is a complete computer system.2. Design and implement the controller and the parallel storage processer.3. For SAT problem and Integer-sharing problem, referring to DNA computing problem-solving model, we instantiate specified dimension processor instances in the FPGA platform and simulated.4. For SAT problem and Integer-sharing problem, colorized graphics display system for quite large dimension was made in PC. The system visually displays the hardware implementation process by simulates real steps.It not only has the advantages of large dimension, high parallelism and complete solution set, but also inherits the features of high precision and high speed from electrical way. Being proved to be effective for some hard problems, it is a meaningful try for solving NP-complete problems in polynomial time.