FPGA Design Of The Pure Integer Arithmetic Parallel Turbo Encoder And Decoder

Turbo codes have been proposed for more than twenty years,in the field of channel coding Turbo codes have achieved an irreplaceable position.In the 5G upcoming today,inherit the past and forge ahead into the future,Turbo codes play an important role,it is of great significance to realize the smooth transition from 4G to 5G.This paper takes FPGA as the design object,to study a new type of parallel Turbo decoder based on pure integer arithmetic,which seeks innovation in the background of the times,and caters to the development.This paper firstly introduces the structure and principle of Turbo coding and decoding,some commonly used simplified class MAP decoding algorithms are compared and analyzed by simulation;then,this paper studies the pure integer linear Log-Map decoding algorithm,and compared with the floating-point Log-Map algorithm and MAP algorithm,the simulation results show that the decoding performance is comparable to the floating point MAP algorithm,It is a kind of practical algorithm which has good decoding performance and is suitable for hardware processing;Due to the high delay of serial iterative decoding,this paper analyzes the sliding window algorithm and two kinds of different initial processing methods of parallel decoder structure,simulation analysis the decoding performance of different window length and different block number,so that to lay the theoretical foundation for the design of the FPGA below.Based on the previous research,the design environment using Altera's Quartus II and the programming language using Verilog HDL,In FPGA design,making full use of pipeline structure and parallel structure to optimize design timing.Firstly,the turbo encoder is designed,each module has been carried out to verify the function and the design results are given.Then,a detailed design of FPGA according to the pure integer block parallel decoding algorithm is completed,also gives the design scheme and the timing simulation map of each module.Finally,the function of the decoder is tested and the equivalent performance is tested.The results show that the design can complete the corresponding function correctly.This paper is divided into four chapters,the first chapter introduces the Turbo code in the history of channel coding,as well as related research of the status quo at home and abord;In the second chapter,on the basis of analyzing the principle of Turbo encoding and decoding,the linear Log-Map algorithm is introduced.In the third chapter,the pure integer linear approximate Log-Map algorithm is integrated into the sliding window and the block parallel decoding structure.The fourth chapter gives the detailed FPGA design and result analysis of the Turbo encoder and decoder.