Research On High-Performance Computer I/O Bus

Computer I/O bus is mainly applied for efficiently connecting CPU and computer pheripheral componets. I/O bus history now has finished the first step of the transition from the the second generation to the third. PCI Express is the mostly important deputy for the third generation I/O bus and has already showed very good adaptability and flexibility, which make it attractive in the market.This thesis mainly covers theoretical analysis of PCI Express technology, practical PCI Express device development and realization of a high-performance data transaction method. At the beginning, computer I/O bus overview is given, and the main research topics in the coming parts are also listed. The second chapter introduces and analyzes the the architecture and principle of PCI Express technology, meanwhile the key points for PCI Express development are abstracted. Together with the key points got in former parts, chaper three describes the PCI Express development scheme in this research, which includes PCI Express x1 lane high-speed interface design, local bus interface design and an optimzed DMA transaction method for PCI Express devices. The forth chaper presents PCI Express device WDM driver technology analysis and gives out a general WDM driver development method for PCI Express devices. Performance testing, analysis and evaluation for the PCI Express hardware, driver and data transaction method in this research will be given in the last chapter, final conclusion will also be achieved then.Debugging and experiment results show that theoretical research of PCI Express technology in this research assists the later PCI Express device development very well. Performance Evaluation shows that the PCI Express communication card developed in this rearch can achieve a very good data transaction speed in either transmission or receive direction, and is better than the widely-applied PCI bus nowadays.