Design And Research Of BRAM Applied To Nano-scale Field Programmable Gate Array

The Xilinx company officially launched the first field programmable gate array( Field Programmable Gate Array, FPGA) in 1985, since FPGA has experienced rapid development. Direction of FPGA chip is very rich, due to the continuous development of modern semiconductor technology, the size of the FET as the FPGA chip, the basic constituent elements decreases rapidly,making FPGA chip integration is increasing.With development levels of integrated circuit design, we access speed of memory, storage capacity requirements are also increasing. Therefore, this paper analyzes the basic architecture of the Xilinx Virtex FPGA Series, the use ISE9.1 and candence development software, using 65 nm process design of a capacity of 36 Kbit memory block( Block RAM, BRAM), focused on the design of the BRAM the main circuit unit, including static memory cells.This paper describes the architecture and development status of the overall FPGA chip and FPGA chip BRAM, and pointed out the importance of programmable memory module BRAM. Secondly, to achieve design capacity of 18 K BRAM circuit module. Capacity 18 K BRAM can be configured as a single-port RAM, dual-port memory structure common RAM, the contents of the address memory, etc., is a major part of the FPGA chip various storage functions. FPGA chip programmable logic(Configurable Logic Block, CLB)and BRAM block memory provides the user a variety of storage resources.On this basis, this paper gives ten million gate FPGA chip capacity, as well as the specific features 36 K BRAM implementation. The module supports multiple addresses and data bits wide aspect ratio combinations, multiple read and write interface bandwidth interface data conversion, support parity bits are written and read out. At the same time, the module adds integrated FIFO control logic and integrated ECC control logic functions.Eventually, on the basis of research and analysis capabilities and implementation BRAM on peripheral circuit BRAM module’s design and research, to achieve the design and simulation of the entire BRAM module functional verification million gates FPGA chip level. The simulation results show that the proposed design in line with the capacity of 36 K BRAM ten million level FPGA design.