Low Power Design Of UHF Passive RFID Chip Baseband

RFID (Radio Frequency Identification) is a technology that incorporates the use of electromagnetic or electrostatic coupling in the radio frequency (RF) portion of the electromagnetic spectrum to uniquely identify an object. In recent years, it has been widely used in the worldwide, including transportation management, intellective traffic, check on work attendance, monitoring of goods, science, medical, and so on. But these applications bring a new challenge to the design and develop of RFID. Whether a product is mobile or not, low power is one of the desired features to the modern IC designs. It is becoming harder and harder to maintain the performance and decrease the power of the design. The low power design methodology involves the entire design flow, and must be adequately verified. The digital baseband design is very sensitive to the power dissipation, especially in RFID passive tag design. So in EPC 10008-6C specifications, low power becoming to be the emphases and focus of the baseband design.This article focus on Low Power Methodology, analysis constitutes of power dissipation, and presents some key low power methods in baseband design. Taking these basic knowledge as a foundation, we will take apart in the several design steps and the physical phase. And we give out design architecture of EPC 10008-6C, and methods suitable to the low power design of RFID. As a key feature of Baseband design, we implement several power management strategy and power optimization techniques, e.g. power management unit, clock gating, low threshold library, and so on. And we get the power of baseband design lower to a level that can be accepted.