Automation Placement And Routing Algorithms On FPGA

The development of micro-electronics, especially the appearance of programmable logic devices, speed the development of the electronic design technology. The core of the modern electronic design technology has turned to the electronic design automation technology based on the computer,i.e. EDA technology. The top-down design flow by EDA technology substitute for the bottom-up design flow,which shorts the development period , reduce the development cost and speed the development of IC. Meantime,The performance of Placement & Route directly influences the reliability of EDA technology. Some methods bettering the performance of the former algorithms of the P&R tool called VPR are proposed, the automation route algorithm is the main research aspect. Among the tool called VPR, SAA(simulation anneal algorithm) is used in the Placement part and the A star iteration heuristic algorithm in Route part.This paper starts with the engendering background, developmental history and relative technologies of FPGA & EDA, then lists the methods used to improve automation route algorithm as follows: to speed up automation placement and route tools, an improved algorithm for bidirectional heuristic algorithm into timing-driven routing algorithm is presented; Net Order Method was proposed and put in timing-driven routing algorithm, meanwhile discussing the influence on routing by ordering methods of the nets: sort ascending and descending separately ;To improve FPGA timing-driven route performance ,the author put area constraint into heuristic cost function.By anlaysing the testing data, Bidirectional heuristic algorithm can increase the routing speed; Ording the nets by sort ascending is more effective than that by sort ascending;Applying area constraint to timing-driven routing reduce the routing area.