Design Of Important Blocks Of Delta-Sigma Fractional-N Frequency Synthesizer

This paper is focused on the design of important blocks (PFD and charge pump) ofΔ∑Fractional-N Frequency Synthesizer. The structure of PFD, whose delay part was separated from the reset part, removed the dead-zone and decreased the gain inversion region simultaneously. Charge pump circuit was proposed with a differential input structure and a dummy current branch, which solved the affections of the charge injection and the gain mismatches. Then the output spur was reduced. Cascode structure for the current references reduced the voltage consumption and enhanced circuit matching. A unit-gain amplifier was used to equate the voltage of the dummy branch and the output branch in order to eliminate charge sharing. The design was completed include circuit simulations, layout, and being taped out base on chartered 0.35um RF CMOS process.Aiming to enhance the performance of the Fractional-N Synthesizer, charge pump needs a 20u stable current reference. This paper designed both a first-order and a high-order compensated current reference with near zero temperature-coefficient, which were designed based on TSMC 0.25um process. The current reference composed by a bandgap core circuit, operational amplifiers (OTA), and startup circuit. Results of high-order compensation showed that it had a limited temperature drift and high power supply rejection ration (PSRR): temperature-coefficient was about 5ppm/℃over a large temperature range from -20℃to 150℃; the PSRR was 93dB for frequencies below 10kHz and more than 60dB before 2MHz.