900mhz Cmos Frequency Synthesizer Phase-locked Loop-based Structure Design

Because of the rapid development of the wireless communication technology, the design andresearch of the integrated circuits in the related field has gained more and more attention in recent years.And with the advance of the IC process technology, the cutoff frequency (fT) of MOS devices can reachseveral giga herz or more. It is a trend that CMOS process will replace the III-V compound processsuch as gallium arsenide (GaAs) or silicon bipolar process which were dominant in the fields of radiofrequency (RF) and microwave. Since baseband signals are processed in the digital domain, and mostof all digital integrated circuits are manufactured using CMOS technology nowadays, if radiofrequency circuits are also designed and manufactured using CMOS, it is possible to integrate the RFanalog part and baseband digital part in one chip. This is very attractive, and also in conformity withthe development tendency of silicon on a chip (SOC). Frequency synthesizer, which is one of the most important building blocks of the transceiverfront-end, is used to generate local oscillation signals. The design of the frequency synthesizer is alsovery complex and difficult. In this work, a PLL-based CMOS fractional-N frequency synthesizer isdesigned according to the GSM (900MHz) standard. The contribution of the dissertation is generalized as following: 1) The systematic model of the third-order charge-pump PLL-based frequency synthesizer isanalyzed, and some guidelines of the circuit level design can be obtained from this system analysismodel, 2) It is found that the phase noise of the VCO dominates the noise performance of the wholesystem through the analyses of the noise transfer functions of each building block of the frequencysynthesizer. In the applications of radio frequency range under super-deep sub micron CMOS process,there may be nonlinearity problem when high order differentiation is taken by using traditional MOSmodel (such as BISM). In order to overcome this problem, we propose a new nonlinear phase noiseanalysis model which is adapt to computer-aided analysis. This phase noise model is based on theAbstractsurface potential model of MOS devices, and solved by ODE-PDE combined method. 3) In the circuit design, several novel and improved architectures are proposed, including: an LCVCO with partial tuning by using switched-capacitors, a charge-pump circuit with adjustable outputcurrents which is insensitive to the changes of external power supply and temperature, a high-speedmulti-modulus prescaler and a loop filter with a novel initialization circuit. With switched-capacitors tofulfill partial tuning, only one VCO is needed to cover transmit and receive path and skip the uselessgap between; with adjustable charge-pump currents insensitive to the changes of external power andtemperature, the system performance can be changed accordingly, and the noise characteristics can beimproved; the initialization circuit of the loop filter can speed up the system when power on; and themulti-modulus prescaler can expand the frequency coverage of the frequency synthesizer. The circuit is designed using SMIC's 0.18μm 1P6M standard digital logic CMOS process. TwoVCOs with different structure are manufactured and tested. Some desired performances are achieved.