Research On Application Of Boolean Process In Delay Analysis And Waveform Simulation

With the incessant development of VLSI technology, the design of complex and high-speed chips impulses the evolvement and improvement of theories and algorithms in design automation. As a language which describes digital circuit and designs digital logic system in formalized way, HDL has been enriching and optimizing its syntax and semanteme. Additionally, Boolean process, proposed recently, provides us with new theory foundation to consummate and improve the old algorithms and models.The theory of Boolean process is an analytical approach to represent circuit with mathematical formula, which combines logic function with delay properties of digital integrated circuits to express circuit states in continuous time nodes by waveform for the help of exact timing analysis. This dissertation will discuss new methods in delay analysis and logical waveform simulation based on Boolean process.Firstly, several crucial problems and pretreatment algorithms in the simulation process are explained in detail, containing the gate-level delay models used in Boolean process, the sort arithmetic solving partition of combination logic, algorithm confirming the minimum clock circle, the cycle-based method for synchronous sequential circuits, check and management of competition and narrow pass, etc.For logic waveform simulations, a waveform presentation method based on Boolean process is described by hardware description language Verilog HDL and VHDL.During delay analysis, a method of delay matrix based hierarchical delay analysis is improved in this paper. Firstly, studies on an analytical delay model based on Boolean process are made. Based on this concept, sensitization defined delay matrix is proposed to describe the delay of circuit modules. Secondly, circuits are comparted hierarchically. Finaly, after operations of expandment and superposition are made on delay matrix of every module, delay of the whole complex ciucuit is computed conveniently, a novel exact hierarchical delay analysis method is presented.To verify the correctness and validity of this method, examples of a combinational circuit and a sequential circuit are simulated with analysis of the results. The fact that the approach can greatly reduce the computation time on complex problems with good exactness and high precision is proved by experiments.