Memory Architecture Design For Liquid Crystal Display Controller

LCD controller is a graphics and image displaying control chip for liquid crystal display applications. It is designed to provide synchronous control signal and display data to the LCD panel with data processing function. For recent years, liquid crystal display system is widely used in hand-held devices. Therefore LCD controller has been integrated with more and more functions and low power consumption is regarded as the most important mission of LCD controller chip design.As the demands for display effects increase, display systems require LCD controller with larger display memory. Display memory also called frame buffer, it is the most important part in LCD controller. The performance and application field are decided by the architecture and capability of its display memory. Based on the analysis of LCD controller architecture, this dissertation presents two new display memory architectures for LCD controller. One is compressing display data architecture with self-adaptive run-length encoder. Through compressing display data in display memory, the architecture has the function of saving memory space and chip power consumption. The other architecture is external memory by using SDRAM controller. Implementation methods and simulation waveform for both architectures were provided in this dissertation after theory and operations had been discussed. Some pivotal issues such as arbitrator, address decoder are also analyzed. We use FPGA to verifying the LCD controller with new memory architectures and the LCD controller are synthesized in 0.18μm CMOS process. Power analysis and optimization, FPGA verification and synthesis results are provided in the last two chapters.The design follows the top-down design flow and the RTL code of LCD controller chip is described by using Verilog HDL. In succession, the function verification and the implementation with various EDA tools are presented. The architectures are proved to meet the expected performance and design requirements through the FPGA verification, synthesis and power analysis.