Research On Low Power CMOS Integrated Circuit Design

The integration level and performance of integrated circuit have gained enhancement with the development of submicron, deep-submicron and system on chip technology in recent years. Meanwhile, the increase of system complexity and the wide application of various mobile devices make low power a chokepoint, which plays an important role in the development of integrated circuit design. Low power design has become a principal indicator that used to measure electronic product performance. Nowadays, CMOS integrated circuit design technology has been widely applied in the design of low power. High performance and low power CMOS integrated circuit design has been a focus of integrated circuit design.This paper first analyzes the power dissipation mechanism of CMOS circuit according to quiescent power drain and kinetic power drain. Different power dissipations are modeled and several optimizations are discussed.Secondly, this paper designs a bandgap reference voltage source circuit, which employs resistive subdivision and subthreshold technology. It reduces not only output voltage but also power voltage. As a result, the circuit power dissipation is reduced and the low power requirement is satisfied.Thirdly, this paper also analyzes the low power design approach that used to reduce threshold voltage. Based on bulk-biased and quasi-floating-gate technology, this paper presents a circuit design to lower the requirement of circuit on power voltage. The design is simulated and validated by using two-stage operational amplifier circuit. The simulated results show that maximum open-loop gain of the operational amplifier is about 72.5dB, unit gain bandwidth is 1.5MHz, phase margin is 53°, quiescent power drain is 148μW. The basic design requirement of operational amplifier is achieved.