Research On The Key Technology Of Gate Driver Integrated Circuit For GaN Power Devices

Constantly innovations for high-voltage power devices and gate driver ICs promote the rapid development of power system.At present,the improvement of power efficiency has slowed down as the silicon power devices approach its theoretical limit.Replacing traditional silicon power devices with GaN power devices is becoming an effective way to break through the bottleneck of power system performance.However,due to the characteristics of fast switching speed,low gate breakdown voltage and large reverse freewheel loss,GaN power devices cannot be efficiently and reliably controlled by traditional high voltage gate driver ICs.Therefore,it is urgent to develop the application-specific high-voltage gate driver IC for GaN power devices.But it is difficult to improve the transmit speed,protect the gate intelligently and reduce freewheeling loss with optimized dead-time when design GaN gate driver.In view of the above technical difficulties,these techniques such as transient noise immunity technique,gate clamp technique and adaptive dead-time have been studied in this thesis,leading to some corresponding innovative methods.In addition,the design is verified based on the domestic700V high and low voltage compatible BCD process.The main works and innovations are concluded as follows:1.The mechanism of chip signal disturbance caused by the transient dVs/dt noise have been studied deeply.The contradiction between transient noise immunity capability and propagation delay is emphatically analyzed.It is points out that filtering out the differential mode noise is the key to optimizing this contradiction.A high voltage level shifter with dual-interlock technique is proposed in this thesis.Experimental results show that the gate driver IC's propagation delay is lower than 25ns and the dVs/dt capability is greater than 100V/ns.2.A gate protection technique with bi-level bootstrap circuit is proposed in this thesis.In order to prevent the bootstrap capacitor from overcharging,a voltage signal from negative voltage sensor is utilized to control the charging path of bootstrap capacitor.A bilevel isolated bootstrap circuit is utilized to extend the output voltage range of level shifter which improves the chip's allowable negative Vs bias capability.Experimental results show that the allowable negative Vs bias capability of the proposed gate driver can reach-6V at 5V power supply,leading to more than 20%improvement in FOM.3.An adaptive dead-time technique with dynamic stepped delay generator is proposed.The value of delay line in deadtime circuit can be adjust adaptively according to the positive or negative states of the switch node at the end of dead-time period.Experimental results show that the minimum value of HO-LO dead-time and LO-HO dead-time are 11.6ns and 8.4ns,respectively.4.A high linearity relaxation oscillator with pre-charge technique is proposed in this thesis.The effect of comparator offset and delay variation across PVT on the operating frequency will be counteracted by the pre-charge process because it is included both in the effective charge process and the pre-charge process.The experimental results show that the linearity of the oscillator reaches 99.41%.5.Completed the analysis and design of other key circuits of the gate driver IC for GaN power devices,such as the input stage circuit,output buffer with small dead-time,under voltage protection circuit and etc.Based on the research results of these key circuits,a 600v high voltage gate driver integrated circuit is developed.Moreover,the propagation delay,switching characteristics and protection function are measured.