Study Of Code Optimizing Method Based On Parallel Functional Units

Compared with traditional DSP, modern DSP use more ILP technologies to improve its performance. The DSP we discuss in this thesis uses a clustered VLIW architecture and can perform multiple operations simultaneously during a single clock cycle .we discuss the construction of the code optimizer of VLIW DSP and present the implementation of TI TMS320DM642 especially.VLIW DSP code optimizer is implemented based on LCC compiler framework. First, we get the intermediate code from LCC frontend. And then we select instruction of target machine by template matching for intermediate code. Finally, we get assemble code that can be parallel processing. by cluster assigning,instruction scheduling and register & functional units assigning simultaneously.We customized a machine specification and a machine description for VLIW DSP. We write iburg specification which contains code generating rules, and iburg reads the specification and generates the instruction selection code. It improves the VLIW DSP code optimizer's retargetability.One prominent features of our DSP' architecture is clustering. With this feature, an important phase of our code optimization is cluster assigning, which maps operations and their operands to appropriate clusters. Cluster assignment should make maximal use of functional units across clusters, and reduce inter-cluster data movement besides. We discuss traditional cluster assignment algorithm and LIST instruction-scheduling algorithm, and implement the Unified Assign Schedule (UAS) algorithm to support cluster assignment, which has the following features: cluster assigning and scheduling are unified, and when scheduling an operation, the operation and its operands are assigned to their appropriate clusters at the same time. Experiments show that the code optimizer in this thesis is very effective in optimization of classical DSP Algorithm...