Design And Implementation Of A VLIW DSP Assembler And Code Generator

Compared with traditional DSPs, modern DSPs use more ILP technologies to improve their performance. On the other hand, they present regular and compilable architectures, which enable construction of efficient, optimizing compliers for them. In this thesis we discuss such a DSP, which uses a clustered VLIW architecture and can perform multiple operations simultaneously during a single clock cycle. We describe the construction of the assembler and the code generator of VLIW DSP.To ease the processing of forward references, our assembler is organized as a two-pass structure. In the first pass, it only records information about symbols (labels) in the source file. In the second pass, it scans the source file again, and by using the information collected earlier generates the object file. The VLIW DSP assembler's features include: it uses lex and yacc to generate the lexer and the parser respectively; an assembly statement exists as an internal representation in the assembler; instructions' encoding information is saved in the data tables, and when encoding an instruction a generic procedure is employed to search these tables to decide on its encoding format and opcode, and then a corresponding encoding function is called to produce its machine code.Our code generator is implemented based on IMPACT C compiler framework. We customized a machine specification and a machine description for the VLIW DSP, and constructed the code generator using the template provided by IMPACT. One of the prominent features of our DSP's architecture is clustering, that is, a big centralized register file is splitted into more small pieces, each and its several associated functional units forming a cluster. With this feature, an important phase of our code generation is cluster assigning, which maps operations and their operands to appropriate clusters. Cluster assignment should make maximal use of functional units across clusters, and reduce inter-cluster data movement besides. We implemented the Unified Assign and Schedule (UAS) algorithm to support cluster assignment, which has the following features: cluster assigning and scheduling are unified, and when scheduling an operation, the operation and its operands are assigned to their appropriate clusters at the same time.