Research And Hardware/Software Modeling Of MIPS32^TM Compatible Processor

The front-end design of a processor integrated in an SOC is represented in the form of IP core, an RTL model using hardware description language. Based on a detailed study on 32-bit MIPS architecture, software and hardware models of MIPS processor are established respectively using C language and Verilog HDL.The thesis first discusses some advanced technologies used in the design of microprocessor architecture, such as parallelism, cache and branch prediction. A CPU architecture emulator is proposed after studying MIPS32TM ISA and the according software compiling process. The hardware behavior of a CPU is described using C language. CPU emulator on a software basis helps exploring microprocessor architecture as well as hardware implementation.In Chapter 5 the base of hardware modeling is established, first with the introduction of the general ASIC and SOC design flow, in which software / hardware modeling and FPGA verification are of extreme importance. Then the bus scheme exploited in this design is presented. In Chapter 6, a hardware processor model compatible with MIPS32TM ISA is proposed. This model comprises six-stage pipelined data path, controller, memory system and branch predictor, etc. The impact of the order of pipeline on the performance of the processor, and the solution to pipeline hazard is discussed after that. In the last part, verification scheme involving function simulation and FPGA verification is investigated. In addition, SOC design and verification based on the proposed soft core is discussed.This design is called OCMIPS and includes three versions of hardware model which are all six-stage pipelined and compatible with MIPS32TM ISA. OCMIPS V1.0 is equipped with a static branch predictor, it can run C program and has passed FPGA verification. OCMIPS V2.0 integrates type-configurable dynamic branch predictor, and it also can run C program and passed functional simulation. OCMIPS V3.0 integrates both type-configurable dynamic branch predictor and 2-way set associative cache, has passed functional simulation and some assembly program testing.Six-stage pipelined datapath is explored based on analysis of traditional five-stage piplined datapath's timing bottleneck. Synthesized by Synplify Pro 8.1, OCMIPS V1.0 is able to run at up to 80MHz, with cost of 3386 LUTs (47%) on XC3S400-PQ208 FPGA chip.