0.18μm CMOS High-Speed Low-Power Demultiplexer

With the rapid development of telecommunication networks, computer networks and Internet, it is urgent to build information highway. Optic-fiber communication systems are the principal and important parts of modern communication for its merits such as great capacity, long transmit distance, economizing energy source, anti interference and anti radiation etc.Demultiplexer (DEMUX) is a key circuit Optical-fiber communications. As the back end of optic-fiber receiver, DEMUX decomposes a high-speed data stream to several original low-speed data streams.With the sharp development of deep submicron CMOS technology nowadays, the minimum dimension of MOS gate decrease gradually, which leads to higher characteristic frequency. Now many foundries supplying such technology are established. With the prominent advantages of low cost and high stability, deep submicron CMOS technology are more and more popular in high speed high performance integrated circuits research.This paper presents a 0.18μm CMOS demultiplexer for SDH STM-64 optical receiver. The system is constructed in tree parts including a high speed 1:2 DEMUX cell, two low speed 1:2 DEMUX cells, divider, input and output buffers for data and clock. To realize lower power dissipation, a latch structure with a common-gate topology and a single clock phase is utilized in the high-speed 1:2 DEMUX cell, while dynamic CMOS logic in the low-speed 1:2 DEMUX cell. Measured results at 10Gb/s by 231-1 pseudorandom bit sequences (PRBS) via on-wafer testing indicate that it can work properly with the power dissipation less than 100 mW with 1.8 V supply. The die area of the DEMUX is 0.65×0.75 mm2.Further research was conducted after summarizing experiences in last chip designing. A 20Gb/s 1:2 DEMUX was fabricated in TSMC 0.18μm CMOS technology with 49GHz characteristic frequency. Primary measured results show excellent performance, correct logic at 20G/s input data rate, max operating data rate of 22Gb/s, power dissipation of 108mW with 1.8V power supply. The die area is 0.48×0.59mm2.Circuit design, layout drawing, tape-out and measurement of these two chips are presented primarily. Then detailed analysis of the measurement results is given. And, improved scheme is proposed at last.